Your mission
Location: Stuttgart, Germany
Type: Full-time, hybrid (1–2 days remote work per week)
Level: Principal / Distinguished Engineer or Architect
Your mission
The future of AI computing is light, not electrons.
Q.ANT is building photonic processing systems that compute with light – delivering a scalable, energy-efficient alternative to transistor-based architectures for next-generation AI and HPC applications.
As Principal ASIC Architect – Photonic AI Processors, you will define the architecture of our digital processor that controls photonic integrated circuits for AI training and inference. Working with a third-party ASIC implementation partner, you'll provide technical leadership to internal photonics, firmware, and system integration teams, translating cutting-edge photonic requirements into a processor architecture optimized for high-bandwidth, low-latency control of our photonic computing platform.
What makes this role unique
- High complexity: Integrating processor architecture with novel photonic device control paradigms – an area with few industry precedents where you'll define how light-based computing is orchestrated at the instruction level.
- Strategic freedom: Broad autonomy in selecting design methodologies, architectural approaches, and IP building blocks, constrained only by high-level product and business goals.
- Decision authority: You define the technical direction for processor architecture, influence make/buy decisions on IP, and approve final architectural trade-offs.
- Innovation mandate: Create novel architectural features that will become differentiating IP for the company – your designs will define how photonic processors operate.
- Real-world impact: Your work directly enables technology already deployed in production at world-leading institutions like the Leibniz Supercomputing Centre.
Your Impact & Responsibilities
Your impact
Within your first 18–24 months, you will:
- Deliver a processor architecture optimized for high-bandwidth, low-latency control of photonic integrated circuits in AI training and inference systems that achieve up to 30x energy efficiency vs. conventional systems.
- Ensure the design meets aggressive performance, power, and integration goals to maintain competitive advantage in the rapidly scaling photonic computing market.
- Optimize architectural trade-offs to reduce implementation cost and time-to-market without compromising performance.
- Achieve first-silicon success through accurate modeling, verification strategy alignment, and close partner collaboration.
Key responsibilities
- Provide technical leadership to internal photonics, firmware, and system integration teams, as well as to the external third-party ASIC/processor design partner.
- Define and manage processor architecture milestones, aligning with overall product roadmaps and photonic IC development timelines.
- Act as the primary technical interface between internal R&D, product management, and the external implementation partner to ensure requirements are fully translated into the processor design.
- Guide less experienced engineers in digital architecture and design principles relevant to photonic systems.
- Identify architecture-level risks early, coordinate mitigation plans, and escalate critical blockers to management.
- Define complete processor architecture specifications within agreed timelines.
- Integrate photonic-specific control features seamlessly into the processor instruction set and memory hierarchy.
- Build up and manage a team for future implementations.