The future of AI computing builds on light. Q.ANT is building photonic processing systems that compute with light – delivering a scalable, energy-efficient alternative to transistor-based architectures for next-generation AI and HPC applications.
 
We are looking for a mid-to-senior level engineer to join our team. As the technical owner of PIC design, you will own the end-to-end design and tape-out of integrated photonic circuits – from circuit definition through layout integration, verification, and release. You will ensure every chip is testable, manufacturable, and ready to scale, while directly shaping Q.ANT's photonic technology and product roadmap.


What You Will Do

• Own and drive end-to-end tape-outs: lead circuit coordination, layout integration, DRC sign-off, documentation, and release readiness across multiple concurrent projects
• Act as the primary interface to foundries and external fabrication partners – aligning designs to process constraints, resolving design rule conflicts, and ensuring correct execution
• Contribute to PDK development and validation, and continuously improve the design workflow through automation, layout reuse, and review practice improvements
• Mentor junior engineers on photonic layout, verification, and tape-out best practices; spread a culture of rigour and ownership across the PIC team
• Feed design insights into Q.ANT’s photonic technology roadmap, proposing new components and optimisation strategies